The present invention relates generally to improvements in clock generation circuitry for pipeline analog-to-digital converters (ADCs), and more specifically to improvements for reducing the amount of switching noise in delay lines of delay locked loop (DLL) circuits in such clock generation circuitry and to provide additional available tap points in the DLL circuits.
FIG. 1 is a diagram of a prior art pipeline ADC which typically is clocked by the conventional clock generation circuitry of FIG. 2. The prior art pipeline ADC includes a sample and hold amplifier (SHA) which receives an analog input I/P. The output of the SHA is connected to the input of a pipeline stage 1, the output of which is connected to the input of a pipeline stage 2, and so forth for the remaining stages of the pipeline ADC. The SHA and pipeline stages 1, 2, etc. are clocked by a main clock signal CLK which is routed from the last stage, in the direction opposite to the signal, to the first stage, and the gain stages of each of pipeline stages 1, 2 etc. are clocked by sample signals S and SP and by hold signal H. The gain stages typically include two-stage Miller-compensated amplifiers. Commonly assigned U.S. patent U.S. Pat. No. 6,400,301 entitled “AMPLIFYING SIGNALS IN SWITCHED CAPACITOR ENVIRONMENTS”, issued Jun. 4, 2002 to Kulhalli et al., entirely incorporated herein by reference, illustrates such a two-stage Miller-compensated amplifier
FIG. 2 shows a conventional clock generator circuit for generating the signals S and H used for clocking a conventional pipeline ADC. (An additional sample signal SP having a slightly different transition time than the sample signal S and an additional hold signal HP having a slightly different transition time than the hold signal H are also typically used.) The conventional clock generator circuit of FIG. 2 receives a main clock signal such as CLK coupled to one input of a NAND circuit 10 and an input of an inverting delay circuit 11. A suitable number of inverting delay circuits such as 12 and 13 are connected in sequence to the output of a NAND circuit 10 to produce the hold signal H, which is fed back to one input of another NAND circuit 14. The output of inverting delay circuit 11 is connected to another input of NAND circuit 14. A suitable number of inverting delay circuits such as 15 and 16 are sequentially connected to the output of NAND circuit 14 to produce the sample signal S, which is fed back to another input of NAND circuit 10. This conventional clock generator circuit suffers from process, voltage, and temperature (PVT) variations and mismatches, which makes it difficult to maintain a sufficient amount of “non-overlap time” between the sample time and hold time, wherein the non-overlap time is the total amount of time available for the pipeline ADC to perform its sample and hold operations (during which the sample signal S and the hold signal H, respectively, are high). The timing diagram of FIG. 3 shows the CLK signal, the sampling signals S and SP, and the hold signal H typically applied to the even stages and odd stages of the pipeline ADC shown in FIG. 1.
The known clocking schemes such as one shown in FIG. 2 have included the use of delay circuits for producing non-overlapping clock signals, but unfortunately the delays produced by such delay circuits have very large PVT (process, voltage and temperature) variations which have resulted in reduced total sample times or hold times, thus providing less time for the switched capacitor amplifiers in the pipeline ADC stages to settle.
A very large amount of switching noise is produced in single delay lines of conventional delay locked loop (DLL) circuits. The delay line of a DLL is simply a chain of a typically large number of delay cells that switch continuously. The continuous switching injects noise (also referred to as “substrate noise”) into the integrated circuit chip substrate. Such substrate noise may adversely affect the performance of other circuitry on the same chip.
Furthermore, some of the tap points of the single delay lines of conventional DLL circuits are connected to “watch dog circuits” which perform the functions of detecting “harmonic lock” or “stuck state” conditions in order to ensure proper working of the DLL loop circuitry. The tap points connected to the watch dog circuits are not available to be also connected to the clock generation circuitry, because in order to ensure matched delays at the output of the DLL, the loading at each output needs to matched, whereas connecting the tap points to inputs of the watch dog circuit results in introducing additional loading that prevents the needed matching. The above mentioned tapping used by watch dog circuits has required the use of cumbersome load matching circuitry to ensure the matched delays in the conventional DLL circuits.
The performance of the above described prior art integrated circuit pipeline ADCs and DLL circuitry have been subject to very large process, voltage, and temperature (PVT) variations.
Thus, there is an unmet need for improved DLL circuitry for generating clock signals in a pipeline ADC so as to avoid large PVT variations of the clock signals and thereby avoid the resulting degradation in performance of the pipeline ADC.
There also is an unmet need for improved DLL clock generation circuitry that makes more delay tap points available for use in generating clock signals while nevertheless allowing watch dog circuitry to provide necessary monitoring and control of the clock generation circuitry.